FPGA technology promises both the high performance of a custom hardware solution with the flexibility of a fully reprogrammable platform. It is hence ideal for computationally intensive and evolving application areas such as digital signal processing, and compute-intensive data processing algorithms. However, the FPGA programming model is normally hardware-oriented rather than application-oriented, and although behavioural synthesis tools have made enormous progress, structural design still results in circuits that are substantially smaller and faster. Hence it is still crucial to use structural design techniques with efficient logic cell use in order to satisfy design area and speed requirements. Although it is possible to use the well-established hardware description languages (e.g. VHDL or Verilog), these are not very suitable for describing structural circuits. Indeed, VHDL structural descriptions tend to be extremely verbose, as detailed wiring has to be explicitly specified even for the most trivial connections. Hence, the code is hard to produce, read and maintain. Moreover, in order to describe placement information in VHDL, vendors add proprietary extensions, which are not part of standard VHDL.
There has been a trend towards the use of high level hardware description notations based on existing high level languages for structural circuit design. Lava for instance is a language based on the lazy functional programming language Haskell, and allows for rapid generation of regular structures (rows, columns, trees etc.) using function composition. This project proposes the development of the next generation of a high-level hardware description environment, called HIDE, which was first developed by the project supervisor, and is part of the aforementioned trend. Central to HIDE is a high-level hardware description notation that allows for structured, parameterised and recursive circuit descriptions in two and three dimensions. This is particularly suitable for regular and highly scaleable architectures as those encountered in image and signal processing. Structured FPGA configurations in EDIF format (and VHDL/Verilog) are generated automatically from such descriptions. The proposed HIDE++ environment will allow for behavioural as well as structural modelling of hardware architectures. It will also include a control path synthesis engine, something of paramount importance in circuit design, as well as a source-level simulator capable of integrating HIDE++ into industry-standard hardware design and modelling tools.
Candidates should preferably have prior experience in compiler design and language transformation.
Supervisor: Dr. Khaled Benkrid
