The aim of this project is to develop a hierarchical library of highly parameterisable and efficient skeletons for FPGA-based video applications. The figure below illustrates the proposed hierarchical library. At the bottom level, the library will provide a basic layer of macros which form the basis of any DSP application including buffers, multipliers, dividers and memory interfaces. Based on this layer, a basic image/video operations library of macros (e.g. for FIRs, DCTs and DWTs) will be developed. At the top level, more complex image/video processing operations (e.g. for JPEG encoding/decoding) will be built. The proposed library will be integrated into a graphical front end for high level video application specification.
The novelty of the work consists in the use of higher order functions (or skeletons) for describing complete applications. These skeletons will include hardware optimisations built into them.
The proposed research project will build on a substantial knowledge base built up by the project supervisor during the past ten years in the area of FPGA-based video processing and skeleton-based hardware design.
Supervisor: Dr. Khaled Benkrid
