Multiple Input Multiple Output (MIMO) wireless techniques were first proposed 10 years ago as a means to significantly improve data rates of radio links. By using multiple antennas at both ends of a wireless link, it is possible for each transmit antenna to send a different packet of information, so that the same set of radio frequencies can be reused several times. These techniques are now being adopted in wireless terminals, notably in the IEEE 802.11n working group, which is standardising MIMO configurations for wireless local area networks. MIMO is also being investigated by the 3GPP standards group for improving the performance of long term evolution (LTE) of third generation wireless systems. This means that the design of efficient, high throughput MIMO transmitter/receiver circuits with good link performance is becoming a key challenge for wireless developers.
The optimum MIMO detection algorithm is called the maximum likelihood decoder, but its complexity increases exponentially with the number of antennas used, making it unsuitable for anything other than the smallest MIMO system configurations. In recent years, the sphere decoding (SD) algorithm has been shown to be a promising alternative detection algorithm, which can achieve maximum likelihood performance with much lower complexity [1]. However, this algorithm uses tree search techniques to find the right solution and the complexity of this algorithm can vary significantly over time due to radio channel and noise effects. Recent work at Edinburgh led to a novel detection algorithm, called the fixed sphere decoder (FSD), which maintains fixed detection complexity with a very small performance loss compared to the SD [2]. This work used Xilinx DSP system generator to port MATLAB designs to an FPGA and demonstrated that the FSD detector could run 2-3 times faster than an equivalent SD circuit.
The aim of this project is to build on the FSD research to investigate how MIMO detection algorithms can be designed and ported onto FPGA devices efficiently. The researcher will focus on two different approaches to tackling these problems:
- I. The design of novel transmitter and receiver algorithms, which are specifically targeted for hardware implementation on parallel devices such as FPGAs. This will investigate further improvements to the fixed sphere decoder algorithm [2], as well as considering alternative options such as detectors based on Monte Carlo methods [3].
- II. Consideration of novel FPGA circuit designs which will enable variable complexity detectors, such as the sphere decoder, to be implemented more efficiently. This includes adaptive circuit designs which can inherently cope with various channel conditions to ensure a desired level of quality of service.
- [1] M.O Damen, H.E. Gamal and G. Caire, “On maximum likelihood detection and the search for the closest lattice point”, IEEE Trans Info Theory, Vol 49, No 10, pp 2389-2402, October 2003.
- [2] See the fixed sphere decoder homepage: www.see.ed.ac.uk/~jst/sphere/ for more information and a list of publications from this project (11 conference papers and 3 submitted journal papers). This work was partly sponsored by Alpha Data Ltd.
- [3] B. Farhang-Boroujeny, Haidong Zhu and Zhenning Shi, “Markov chain Monte Carlo algorithms for CDMA and MIMO communication systems”, IEEE Trans Signal Processing, Volume 54, Issue 5, May 2006, pp 1896 – 1909.
Selected Publications
Supervisors: Dr. Khaled Benkrid and Dr. John Thompson
