Applications (e.g. wireless communication and multimedia) demand high performance, strict low power, and in-field reprogrammability in order to follow the evolving standards. Traditional single-core architectures fall short of meeting all these requirements, since in the past few years, people have not seen great gains, but instead diminishing returns in processor performance through increasing operating frequency (made possible via deeper pipelining) and Instruction-level Parallelism (ILP). It is known that the development of single-core processors hits three walls: memory wall, ILP wall and power wall. Now both industry and academia are all agreed that the continuing increases in transistor count and operating frequency of a microprocessor can no longer make it faster, instead multiple or many simpler processing cores should be put onto a chip. Therefore the processing load of complicated applications can be distributed across multiple processing cores. This delivers more overall performance through parallelism. However one question arising from multi-core architectures is that what kind of processing core would be the best candidate for multi-core architectures targeting embedded applications like WiMAX. Obviously, General Purpose Processors (GPPs) are not well suited to this task, due to their generic feature set and proportion of the silicon for computation. On the other hand, VLIW DSP architectures face the problem due to the limited amount of ILP found in programs. Filling the gap between the high flexibility of DSPs and the high performance of ASICs, Dynamically Reconfigurable processors, such as Reconfigurable Instruction Cell Array (RICA), offer an attractive solution for multi-core architectures.

Current research activities

In SLIg, we are developing multi-core platform using RICAs as the basic processor cores. A SystemC based simulator, called MRPSIM, is devised to model multi-core architectures (both homogeneous and heterogeneous). This simulator provides fast simulation speed and timing accuracy, offers flexible architectural options to configure multi-core architectures, and enables the analysis and investigation of multi-core architectures. Meanwhile a profiling-driven mapping methodology is developed to partition an application into multiple tasks as well as schedule and map these tasks onto the multi-core architecture, aiming to reduce the overall system execution time. So far, variety of applications have been mapped onto the multi-core platform, including WiMAX, AES, FIR filter and image processing applications.